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Under ASIC design implementation & production consulting services AES (ASIC Engineering Solutions Inc.) provides ASIC back-end design services for Physical design layout and place and route (P&R). Our customers include many start-ups, fabless semiconductor corporations and public companies that rely on our on-time fast turn around deliveries.
We have provided layout services for 0.35um, 0.18um, 0.13um and 0.065um technologies for complexities of up to 3 million to 7.5 million gates. We have tape out designs to foundries such as TSMC, UMC, Dong BU, Silterra, and SMIC.
Customers can have peace of mind knowing that by using AES profesional services we will provide world-class design skills, dedicated professional project management, the quality and integrity that reduces the risk and ensure the success and time-to-market of your IC development.
ASIC Design Flow

AES provides the following ASIC implementation and consulting services using Synopsys "ASTRO" layout tool and these others software tools:
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Floor Planning
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Placement and Power Rail Design
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Clock Tree Synthesis
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Routing
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IP Integration
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3-D Parasitic Extraction
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Signal Integrity
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Cross Talk Check and Fix
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LVS/DRC/Antenna check and fixes
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GDS-II Generation
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LVS/DRC can also be performed using Mentor's Caliber
AES provides individuals or teams with consulting for client ASIC projects that help deliver specific application components or fulfill particular project functions. In these situations the customer maintains responsibility and control for project management and deliverables. We can provide project leadership consulting to client's ASIC projects to help deliver specific application components or fulfill particular project functions with our technical professionals assigned to the project. Our project managers perform the role of advisors, facilitators, and the customer retains control and responsibility for deliverables and results.
We offer ASIC design services to clients in high speed high performance computing, networking, graphics and wireless market segments. Our key services include RTL, Netlist to GDS, block level or full chip integration, Design for Test insertion, STA, formal verification signoff services, metal only or all layer ECO and design flow development.
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