AES's Position

• 5 people with 4 Engineers
  • In the center of Silicon Valley
  • Combined 50+ years engineer team
  • 100+ successful chips tape-out experience
• Leading Edge Tool Suites
  • Comple ASTRO tool suite from Synopsys
  • Design for Testability (DFT) tools: Synopsys's Tetramax;
  • Mentor's Fast Scan, MBIST or Syntes's Turbo Scan, MBIST, BSD, etc...

 Management Team

• Luis Castillo, Vice President of Sales
  • 24+ years in Turnkey ASIC/COT srvices
  • Sales Executive at Syntest, Macro Tech Research, Micro Decices Technology LG semi, Toshiba, Intel and Fujitsu Microelectronics.
• George Hung, Silicon Integration Specialists, P&R, Layout.
  • 14+ years in SoC Chip Integration, Physical Design.
• J.T. Prabhu DFT Manager.
  • 14+ years in SoC DFT and Chip Integration.